1. Field of the Invention
This invention relates to a semiconductor device and to a manufacturing method for the same, and more particularly to a structure of a mask ROM (Read Only Memory) in which programming is carried out through the patterning of an isolation insulating film and to a manufacturing method for the same.
2. Description of the Background Art
FIG. 24 is a top view showing the structure of a semiconductor device according to a background art. FIG. 24 shows a two row by eight column section of memory cells, which is a portion of a memory cell array of the mask ROM according to the background art. Word lines WLm and WLn are word lines respectively belonging to the m-th row and the n-th row. A plurality of drain regions 3m that belong to the m-th row are mutually isolated by an isolation insulating film 104 and are formed so as to be aligned in the X direction (row direction) in the figure. In the same manner, a plurality of drain regions 3n that belong to the n-th row are mutually isolated by the isolation insulating film 104 and are formed so as to be aligned in the X direction. A source line SL extends in the X direction between the word line WLm and the word line WLn. The word line WLm extends in the X direction between the plurality of drain regions 3m and the source line SL. In the same manner, the word line WLn extends in the X direction between the plurality of drain regions 3n and the source line SL.
Bit lines BL1 to BL8 are provided for each column so as to extend in the Y direction (column direction) in the figure. In addition, the bit lines BL1 to BL8 are respectively connected to the drain regions 3m via contact plugs 5m that belong the m-th row and to the drain regions 3n via contact plugs 5n that belong to the n-th row.
A ground line GL1 is provided so as to adjoin the bit line BL1 and the ground line GL1 is connected to the source line SL via a contact plug 61. In the same manner, a ground line GL2 is provided so as to adjoin the bit line BL8 and the ground line GL2 is connected to the source line SL via a contact plug 62.
Five memory cells, from among eight memory cells that belong to the m-th row, in which the isolation insulating film 104 is formed between each drain region 3m and the source line SL, are memory cells that memory cell transistors are not formed and correspond to “1” of the ROM code. On the other hand, three memory cells in which the isolation insulating film 104 is not formed between each drain region 3m and the source line SL are memory cells that memory cell transistors are formed and correspond to “0” of the ROM code.
In the same manner, four memory cells, from among eight memory cells that belong to the n-th row, in which the isolation insulating film 104 is formed between each drain region 3n and the source line SL correspond to “1” of the ROM code while four memory cells in which the isolation insulating film 104 is not formed correspond to “0” of the ROM code.
In memory cells that correspond to “1” of the ROM code, the drain regions 3m, 3n and the source line SL are isolated from each other by the isolation insulating film 104. On the other hand, in memory cells that correspond to “0” of the ROM code, the drain regions 3m, 3n and the source line SL are connected to each other via channel formation regions 7m and 7n. 
In FIG. 24, the width of the source line SL with respect to the Y direction is assumed to be W100. In addition, the interval of the contact plugs 5m and 5n belonging to the same column is assumed to be L1.
FIG. 25 is a cross sectional view showing the cross sectional structure with respect to the location along line segment A100—A100 shown in FIG. 24. A P well 9 is formed in a top surface of a silicon substrate 8. In addition, the isolation insulating film 104 is formed in the top surface of the silicon substrate 8 according to a predetermined pattern. A top surface of the isolation insulating film 104 is located above the top surface of the silicon substrate 8. In addition, N+-type impurity introduced regions 12m, 12n and 110 are formed in the top surface of the silicon substrate 8 in the portions that the isolation insulating film 104 is not formed. Cobalt silicide layers 13m, 13n and 111 are respectively formed on the top surface of the silicon substrate 8 in the portions that the N+-type impurity introduced regions 12m, 12n and 110 are formed.
A structure Gm, that sidewalls 16m are formed on the sides of a structure having a cobalt silicide layer 15m formed on a polysilicon layer 14m, and a structure Gn, that sidewalls 16n are formed on the sides of a structure having a cobalt silicide layer 15n formed on a polysilicon layer 14n, are formed, respectively, on the isolation insulating film 104. An interlayer insulating film 17 is formed so as to cover the structures Gm, Gn, the isolation insulating film 104 and the cobalt silicide layers 13m, 13n and 111. A metal film 20 is formed on the interlayer insulating film 17. Contact holes 18m and 18n are formed in the interlayer insulating film 17 and the insides of the contact holes 18m and 18n are filled in with metal films 19m and 19n. The metal film 20 is connected to the cobalt silicide layers 13m and 13n, respectively, via the metal films 19m and 19n. 
In reference to FIGS. 24 and 25, the N+-type impurity introduced region 12m and the cobalt silicide layer 13m correspond to the drain region 3m, the N+-type impurity introduced region 12n and the cobalt silicide layer 13n correspond to the drain region 3n and the N+-type impurity introduced region 110 and the cobalt silicide layer 111 correspond to the source line SL. In addition, the structure Gm corresponds to the word line WLm, the structure Gn corresponds to the word line WLn and the metal film 20 corresponds to the bit lines BL1 to BL8. In addition, the contact hole 18m and the metal film 19m correspond to the contact plug 5m while the contact hole 18n and the metal film 19n correspond to the contact plug 5n. 
Here, though two memory cell structures, both of which correspond to “1” of the ROM code, are shown in FIG. 25, the polysilicon layers 14m and 14n are formed above the silicon substrate 8 via a gate insulating film in a memory cell that corresponds to “0” of the ROM code and, thereby, memory cell transistors (NMOSFETs in the case of this example) are formed to have the structures Gm and Gn as gate electrodes.
FIG. 26 is an equivalent circuit diagram of the memory cell array shown in FIG. 24. The word lines WLm and WLn are connected to a decoder 160 while the bit lines BL1 to BL8 are connected to a sense amplifier pre-charging circuit 161. As shown in FIG. 26, memory cell transistors 150 are formed, respectively, in seven memory cells corresponding to “0” of the ROM code shown in FIG. 24.
In reference to FIG. 26, a read out operation with respect to the m-th row is described. First, in the condition that no voltage is applied to any of the word lines, a voltage is applied to the bit lines BL1 to BL8 by means of the pre-charging circuit 161 and, thereby, the bit lines BL1 to BL8 are pre-charged. Next, after the stoppage of the application of voltage to the bit lines BL1 to BL8, the word line WLm is selected by the decoder 160 and a voltage is applied to the word line WLm.
Thereby, the three memory cell transistors 150 connected to the word line WLm convert to the on condition and, therefore, the charge that has been pre-charged in the bit lines BL5, BL7 and BL8 is discharged to ground lines GL1 and GL2 via the source line SL. On the other hand, the memory cell transistors 150 are not formed in the other memory cells belonging to the m-th row and, therefore, the charge that has been pre-charged in the bit lines BL1 to BL4 and BL6 is not discharged.
Accordingly, after a predetermined period of time has elapsed since the application of voltage to the word line WLm, the potentials of the bit lines BL1 to BL8 are detected by the sense amplifier circuit 161 and, thereby, each ROM code of the eight memory cells belonging to the m-th row can be determined to be either “0” or “1.”
The above described conventional semiconductor device, however, has the following problems.
First Problem
In reference to FIG. 26, a source resistor 151 exists in the source line SL. When the value of the source resistor 151 is great, the voltage drop, which is the product of the on current of the memory cell transistor 150 and the resistance of the source register 151, becomes great at the time of the read out operation. As a result, the efficiency of the discharge becomes poor so that the period of time required for the read out operation increases. In addition, in the case that a synchronous-type sense amplifier or the like is utilized, the ROM code may be mistakenly read out when the detection operation of the sense amplifier is started in the condition where the pre-charged charge is insufficiently discharged. Accordingly, it is desirable for the value of the source resistor 151 to be small.
In the conventional semiconductor device, however, in reference to FIG. 24, the form of the source line SL is a line having a constant width W100. Therefore, when the memory cells of which the ROM code is “1” are sequentially formed, there is a problem that the resistance of the source resistors 151 in that portion becomes comparatively great.
Second Problem
In reference to FIG. 25, in the conventional semiconductor device, the cobalt silicide layer 111 is formed on the N+-type impurity introduced region 110 in order to achieve the lowering of the resistance of the source line SL. This cobalt silicide layer 111 is formed by depositing a cobalt film on the entire surface by means of a sputtering method and by, subsequently, carrying out a heat treatment after the formation of the isolation insulating film 104, the polysilicon layers 14m and 14n, the sidewalls 16m and 16n and the N+-type impurity introduced region 110 in this order.
In the conventional semiconductor device and in a manufacturing method for the same, however, the difference in elevation between the top surface of the N+-type impurity introduced region 110 and the top surface of the polysilicon layers 14m and 14n is comparatively great due to the film thickness of the isolation insulating film 104 in the portions formed above the top surface of the silicon substrate 8 and due to the film thickness of the polysilicon layers 14m and 14n. Therefore, at the time when a cobalt film is formed by means of the sputtering method, the film thickness of the cobalt film that is deposited on the top surface of the N+-type impurity introduced region 110 becomes thinner and, as a result, the film thickness of the cobalt silicide layer 111 also becomes thinner and there is a problem that the resistance of the source resistors 151 increases.